Qualifications

Minimum qualifications:

• Bachelor\'s degree in Computer Engineering, Electrical Engineering, Computer Science, related field, or equivalent practical experience.
  
• 5 years of experience with hardware electronic design automation tools.
  
• 5 years of experience in ASIC chip design.
  
• 3 years of experience in Python/C++ programming.
  
• Experience with writing code and design practices.
  

Preferred qualifications:

• Experience planning and deploying new tools and flows to users.
  
• Experience in AI/ML methods for ASIC development.
  
• Knowledge of chip design processes such as verification, design, and implementation.
  
• Ability to present and explain novel methods to users
  

Summary

• Bachelor\'s degree in Computer Engineering, Electrical Engineering, Computer Science, related field, or equivalent practical experience.
  
• 5 years of experience with hardware electronic design automation tools.
  
• 5 years of experience in ASIC chip design.
  
• 3 years of experience in Python/C++ programming.
  
• Experience with writing code and design practices.
  

Description

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google\'s most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google\'s TPU. You\'ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a CAD Methodology Engineer, you will plan and execute work in an innovative environment, with a focus on providing cutting edge flow and methodology solutions for Internet Protocol (IP) development. You will work with architects, logic designers, and verification engineers to develop flows to build and verify IP\'s and subsystems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google\'s product portfolio possible. We\'re proud to be our engineers\' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Design new Register transfer level (RTL) or design verification methodologies and flows for high performance IPs.
  
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
  
• Be responsible for designing custom RTL or infrastructure solutions for IPs and hierarchical designs, ensuring a delightful experience for our customers.
  
• Work with cross-functional teams and chip leads globally to drive changes.